Signalling circuit



May 9, 1961 D. A. GHERsl SIGNALLING CIRCUIT Filed June 18, 1959 Pzmaom hmm OL.

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SIGNALLING CIRCUIT Dominick A. Ghersi, New York, N .Y., assignor to American District Telegraph Company, Jersey City, NJ., a corporation of New Jersey Filed June 18, 1959, Ser. No. 821,290

24 Claims. (Cl. 340-276) The present invention relates to signalling circuits, and more particularly to signalling circuits of the type used in providing central station electrical protection.

In the protection of property from the hazards of burglary, holdup and other abnormal conditions, one or more electrical protection devices may be provided at the premises to be protected, and the premises may be connected through a direct wire line to a central station, guard station, police headquarters or other central location. The electrical `protection devices at the protected premises are coupled to the line and are arranged automatically to alter the current ilow in the line upon the happening of any one or more particular types of occurrences at the protected premises. Personnel are provided at the central station or other central location to recognize the alteration in current flow in the line and to take appropriate action. Generally, connections from a large number of protected premises terminate at the central station and the central station personnel service all of these premises.

Typically, the electrical protection equipment at the protected premises will respond to an alarm or other signalling condition by opening the line connecting the protected premises and the central station, grounding this line, or, sequentially, both grounding and opening the line. Additionally, special signals such as the socalled police call service may provide for a rapid rate fluctuation in the line current, as by successively opening and closing the line at a rapid rate. The line terminal equipment at the central station must recognize and register the particular alterations in line current so that the central station personnel will be alerted to the existence of the signal transmitted from the protected premises to the central station by alteration of the line impedance.

Since short duration transient potential conditions on a line may simulate true alarm signals, it is desirable that the central station equipment be provided with a time delayed response so that such short duration conditions will not result in spurious alarms. On the other hand, it is desirable that a signal, once registered, re main registered until reset even though the line condition be returned to normal.

Heretofore it has been conventional to provide a double galvanometer movement type instrument (generally called a drop or a central station drop) at the central station for recognizing and registering the signalling alterations in line current. And excellent quality service has been rendered for many years with such electromechanical instruments. However, the electromechanical instruments have been subject to certain deficiencies. For example, in providing a time delay in the registration of signals, it has been difiicult to afford an accurate control of the delay time, especial-ly if capacitors have been provided across the coils, and the delay time has been to some extent dependent on line conditions.

Another difficulty in connection with the electromeastenia Patented May 9, 1961 chanical instruments has been a tendency for interaction v between the galvanometer coils. Again, the electromechanical instruments have had limited service lives and have been basically large -in size, which has been a disadvantage When, as is usual, large numbers of such instruments are mounted in a limited space.

A principal object of the present invention has been the provision of a novel and improved instrument or drop which overcomes the foregoing and other disadvantages which have been encountered in the use of electromechanical drops.

More particularly, it has been an object of the invention to provide a novel and improved drop suitable for use in central station protection sen/ice and which uses only solid state elements.

A further object of the invention has been the pro- 'vision of a drop of the above type which responds within close limits to predetermined line current levels.

Still another object of the invention has Ibeen the provision of a ldrop of the above type in which accurately and easily controllable time delays are provided in registration of line current variations of signalling values.

Yet another object of the invention has been the provision of a drop of the above type which, while aiiording time delays lin the registration of ordinary line signailing current variations, nevertheless responds without delay to a special signalling condition represented by rapid fluctuations in line current of predetermined value.

Other and further objects, features and advantages of the invention will appear more f-ully from the following description of the invention taken in connection with the drawing, which shows one form of circuit arrangement of a drop in accordance with the invention.

Referring now to the drawing, the conductor 10 represents the central station end of the high side of the conductive line leading to the protected premises (not shown). In this case the low side of the line is a ground return shown at 11, but a wire return could be used if desired. Typically, the line 10 will be a leased telephone line and connection to the protected premises will be afforded through one or more telephone exchanges. It is customary to provide equipment at the protected premises which, under normal conditions, maintains the current in line 10 within a predetermined range, e.g., 9-21 ma. Specific values Vof currents and voltages and specific circuit elements are referred to herein for convenience in explaining the operation of the invention, but it should be understood that these speciiic values and specific elements are given by way of illustration only and are not to be construed as in any manner limiting the invention.

Under certain protection conditions at the protected premises the line 10 will be grounded, i.e., the effective resistance at the protected premises between the high and loW sides of the line Will be reduced or shorted out, causing an increase inline current, eg., above 2l ma. Under other protection conditions at the protected premises the line 10 will be opened or broken, i.e., the eiective resistance at the protected premises between the high and low sides of the line will be increased, causing a reduction in line current, eg., below 9 ma. Generally, the line 10 will be of sutcient length that the distributed line constants will cause some current ow even if the line is completely opened at the protected premises.

Under still other protection conditions, the line will be sequentially opened and closed at a rapid rate, e.g., three cycles per second. Under such conditions the line current might uctuate between a value below 9 ma. and a value within the normal line current range, e.g., 18 ma. Such a rapid rate fluctuation in line current is frequently used with a burglar alarm system to provide a distinctive holdup alarm signal.

Line is coupled to the positive terminal of a central station battery 12 through switch back contacts TS1 of a ganged switch S, a line switch 13 (which may, as shown, be part of the ganged switch), the parallel connected windings of potentiometers 14 and 15, and a fuse 16. Central station battery 12, which might be, for example, 30 volts, is the source of current for line 10.v` The negative terminal of battery 12 is grounded. Adjustment of line current to a value within the predetermined range, eg., 9-21 ma., is effected by appropriate adjustment of the equipment at the protected premises. Protection of the drop circuit against voltage surges in line 10 is afforded by providing a diode 17 shunting the potentiometers 14 and 15. Diode 17 might'conyeniently be a Zener diode of the 3.7.8.2 type.

The slider of potentiometer 14 is coupled to the base of a transistor 18 through a resistor 19,.l- Transistor 18 might be of the 2N43 type. The emitter of transistor 18 is coupled to the positive terminal of battery 12 (and the high end of the winding of potentiometer 14)x 'through a diode 20. Diode 20 is preferably a4 Zener (diode since this type of diode becomes conductive at a voltage exactly equal to or very close to its rated voltage and since this conduction voltage is not unduly temperature sensitive. The diode 20 might be of the IN465 type. The collector of transistor 18 is coupled to ground through a resistor 21. Resistor 21 is shunted by series connected variable resistor 22 and capacitor 23. Resistor 22 is shunted by a diode 24, which might be of the IN305 type.

The slider of potentiometer 14 is adjusted so that when n the current in line 10 equals (or exceeds) the minimum current of the normal line current range, the potential across diode 20 will be sufficient to cause this diode to conduct. The conduction potential of diode 20 might be, for example, 2 volts. With diode 20 conductive, transistor 18 will conduct in its saturation range. With transistor 18 conductive, capacitor 23 will charge toward the potential existing between the emitter of transistor 18 and ground. The rate of charge of capacitor 23 will be rapid because of the provision of diode 24 shunting resistor 22. Thus, with a current flow in line 10V at least as great as the minimum normal current, transistor 18 will'be conductive and capacitor 23 will be charged.

If the current in line 10 drops below the normal range, e.g., below 9 ma., the voltage at the slider of potentiometer 14 will be insucient to maintain diode 20 conductive. But with diode 20 nonconductive, transistor 18 will also become nonconductive. When transistor 18 drops out, capacitor 23 will discharge through resistors 21 and 22 at a rate determined by the time constant of the discharge circuit.

The discharge time constant for capacitor 23 may be made any desired value by simply adjusting the value of resistor 22. Typically, the discharge time constant might be adjusted to a time of the order of 0.3 second. The discharge time constant associated with capacitor 23 is not dependent on line conditions but only on the parameters of the discharging circuit, i.e., resistors 21 and 22 and capacitor 23.

The junction of resistor 22 and capacitor 23 is connected to base B2 of a unijunction transistor 25 through a resistor 24. The unijunction transistor 25 might be of the 2N489 type. Base B1 of transistor 25 is connected to ground through manually operable switch 26. The emitter of transistor 25 is coupled to intermediate tap 27 of battery 12 through a lamp 28. A resistor 29 is connected in parallel with lamp 28. Tap 27 might be adjusted, for example, to provide a voltage between tap 27 and ground of 12 volts.

Unijunction transistor 25 will conduct only when its emitter-base B1 voltage equals or exceeds one-half the voltage between its bases. Here the emitter-base B1 voltage is xed by the tap 27, so that conduction or nonconduction of transistor 25 is determined by the potential between its base B2 and ground. But this potential is equal to the potential across capacitor 23. Thus, with capacitor 23 charged, the B1-B2evoltage of transistor 25 will exceed twice the emitter-base B1 voltage and the transistor 25 will not conduct. This is the condition which will prevail with either normal or excess current ilow in line 10.

When the current in line 10. drops below the minimum normal current (9 ma), diode 20 and transistor 18 bccome nonconductive and capacitor 23'starts to discharge. When the voltage across capacitor 23 reaches a value of twice the voltage between tap 27 and ground, in this case 24 volts, transistor 25 will conduct and lamp 28 will become illuminated (through the emitter-base B1 circuit of transistor 25).

illumination of lamp 28 serves as a registration of the fact that the line current has fallen below the minimum normal current and that this condition has persisted for a predetermined time interval dependent on the discharge time constant setting for capacitor 23. Thus, illumination of lamp 28 serves as a break signal. An audible alarm can be provided, if desired, to call the operators attention to the break signal registration.

Should the line current rise to 9 ma. or more before the expiration of this predetermined time interval, diode 2t) and transistor 18 will immediately become conductive and cause charging of capacitor 23 at a rapid rate. In such case the voltage across capacitor 23 would not fall to a value sutcient to render transistor 25 conductive.

Once operated, transistor 25 will remain conductive despite changes in line current. When the operator desires to reset the break signal lamp 28, he opens switch 26, which renders transistor 25 nonconductive. If the line current is still below the normal range, lamp 2S will again be illuminated when switch 26 is reclosed. No time delay will be involved since capacitor 23 cannot recharge until the line current risesV to "the normal range.

The slider of potentiometer 15 is connected to the base of a transistor 30, which might be of the 2N43 type'. The emitter of transistor 30 is coupled to the high side of the winding of potentiometer 15 through a diode 3l which is selected and'poled so as to prevent conduction of transistor 30 until the'voltage at the slider of potentiometer 15 reaches a predetermined level. Diode 3l, like diode 28, is preferably a Zener diode and might be of the IN747 type, which conducts at 3.6 volts. The slider of potentiometer 15 is adjusted so that when the line current exceeds the maximum current of the normal range, c.g., 2l ma., the voltage across diode 31 will be sufricient to render diode 31 conductive and hence also to render transistor 30 conductive.

The collector of transistor 30 is coupled to ground through a resistor 32. The series combination of a variable resistor 33 and a capacitor 34 is connected in parallel with resistor 34. The junction of capacitor 34 and resistor 33 is coupled to the emitter of a unijunction transistor 35 through a diode 36. The transistor 35 might be of the 2N489 type, while the diode 36 might be of the IN305 type.

The emitter of transistor 35 is also coupled to tap 27 of battery 12 through a diode 37 and a lamp 38. The diode 37 might be of the IN305 type. A resistor 39 is connected in parallel with lamp 38. A resistor 40 is coupled between the emitter of transistor 35 and ground. Base B1 of unijunction transistor 35 is connected to ground through a manually operable reset switch 41. Base B2 of unijunction transistor 35 is coupled to the high end of potentiometer 15 through a resistor 42.

With base B1 of unijunction transistor 35 at ground and base B2 at 30 volts (the full voltage of battery 12), unijunction transistor 35 will not conduct until the emitterbase B1 Voltage equals one-half the base B1-base B2 voltage, i.e., l5 volts. But in the absence of a charge on capacitor 34 the emitter-base B1 voltage of transistor 35 will be l2 volts (dueto the connection through lamp 38 S to tap 27). Hence, in the absence of an adequate charge on Vcapacitor 34, transistor 35 will not conduct.

When the line current is below the maximum current value of the normal range, e.g., 21 ma., diode 31 and transistor 30 Will not conduct and capacitor 34 will not be charged. But when the current flow inline 18 exceeds this maximum value, the potential at the slider of potentiometer \15 will be sufficienty to cause diode 31 and hence transistor 30 to conduct. With transistor 38 conductive,

capacitor 34 will start to charge through the base-collector circuit of transistor 30.

The charging rate of capacitor 34 is dependent on the time constant of its charging circuit and not on line conditions, and might be, for example, of the order of 0.3 second. This time constant can be adjusted easily through adjustment of resistor 33. After the iixed time interval provided by the charging time constant of capacitor 34, the potential across capacitor 34 will be sufficient so that the emitter-base B1 potential of unijunction transistor 35 equals one-half the base B1-base B2 potential thereof and transistor 35 will conduct.

Initially, transistor 35 conducts by virtue of the connection of its emitter to capacitor 34 through diode 36. But once conduction is established, the load transfers to the alternate circuit which extends from the emitter of transistor 35 through diode 37 and lamp 38 to tap 27 of ybattery 12. Hence, a fixed time interval after the line current has exceeded the maximum normal value lamp 39 will be illuminated. Illumination of lamp 38 serves as a registration of a ground signal and alerts thecentral station personnel to the receipt of this signal. An audible alarm can be provided, if desired, to signal the personnel of the receipt of the signal. Should the line current drop into the normal range before the predetermined time interval set by the charging time constant of capacitor 34 has expired, diode 31 and transistor 30 will become nonconductive and capacitor 34 will cease charging and start to discharge, preventing registration of a ground signal.

When transistor 35, like transistor 25, has become conductive, it will remain conductive until reset. Resetting may be achieved by manually opening switch 41, thus 'removing ground potential from base B1. When ,switch 41 is reclosed, transistor 35- will again conduct if the line current is still above the normal range.

lThe collector of transistor 18 is`connected to the base of a transistor 43, which might be of the 2N43 type. The collector of transistor 43 is connected directly to ground. The emitter of transistor 43 is coupled to the high end of a battery 45 through a neon lamp 46. An

additional neon lamp 47 is connected in parallel with lamp 46 to afford protection against neon lamp failure. Battery 45 might provide 50 volts. The low end of bat tery 45 is connected to the high end of battery 12.

When the current in line drops below the minimum normal current, transistor '18 will become nonconductive, as described previously. With transistor 18 nonconductive, transistor 43 will become conductive. Since transistor 43 is connected as an emitter follower, the high emitter-collector voltage of transistor 18, when nonconductive, lappears across resistor 44. This voltage across resistor 44 is effectively in series with the bias voltage provided by battery 45, and the combination provides a voltage sufficient to tire neon lamp 46.

When the current in line 10 rises above its minimum normal value, transistor 18 becomes conductive, transistor 43 becomes nonconductive, and the voltage supplied to neon lamp 46 will be insucient to maintain the lamp 46 illuminated. In the so-called police call operation, the current in line 10 will be caused to fluctuate between a value below the minimum normal current and a value within the normal current range at a rapid rate, e.g., 3 cycles per second. Each time the line current exceeds the minimum normal line current, transistor 18 becomes conductive, transistor 43 becomes nonconduetive, and lamp 46 is extinguished. Each time the line current falls below anaemia the minimum normal line current, transistor 18 becomes nonconductive, transistor 43 becomes conductive, and lamp 46 is illuminated. Thus, with the line current pulsating at a rapid rate, the neon lamp 46 will be illuminated and extinguished successively at the same rate. No time delay is provided in the pulsations of lamp 46 as is provided in the case of lamps 28 and 38. Pulsations of lamp 46 serve as a registration of the corresponding signal in line 10 and alert the central station personnel to the existence of the corresponding condition at the protected premises. If desired, an audible alarm may be operated in conjunction with neon lamp 46. The police call signal lfrequency should be suiiiciently high that lamp 28 will not be illuminated.

The batteries 12 and 45 may, of course, be replaced with other suitable sources of D.C. potentials.

SwitchTS1 in the circuit of line 10 has previously been mentioned. This switch forms part of a three position ganged switch S. The switch S has a number of armature-contact sets, some of which are designated LS and some of which are designated TS. In the arrangement i1- lustrated, switch 13 is ganged with and forms part of switch S. In the normal operating position of the switch S, the LS and TS contacts and switch 13 are in the positions illustrated in the drawing. In -a rst test position of the switch S, the LS contacts and switch 13 change condition. In a second test position of the switch S, the LS contacts and switch 13 retain their changed conditions of the iirst test position and in addition the TS contacts change condition.

The iirst test position of the switch S is provided to accommodate periodic testing at the protected premises, for example, as part of routine maintenance. In this position contacts LS1, which are included in the base B1 ground circuit of transistor 35, open to prevent conduc tion of transistor 35 and operation of ground drop lamp 39 if the line current rises above the normal range. This may occur since, although switch 13 is open in this test position, a separate switch 13 shunting switch 13 will normally be manually closed for test purposes. Contacts LS2 close, maintaining a charge on capacitor `23 and hence preventing conduction of transistor 25 and opera tion of break drop lamp 28 even though the line current falls below the normal range. For this purpose, contacts LS2 connect the rectifier 24 directly to the positive terminal of battery l12 so that the battery potential will be available to maintain the charge on capacitor 23.

Also, in the iirst test position of switch S, contacts LS3 operate to their front position, coupling neon lamp 46 to ground through a resistor 49. With this connection, batteries 12 and 45 are in series with lamp 46, which will remain illuminated until contacts LS3 are returned to their back position. Continued illumination of lamp 46 remindsthe central station personnel that the testing condition at the protected premises is sti-ll in eect and that no protection is being afforded.

In the second test position of switch S, the various contacts LS and switch 13 retain their positions as described for the iirst test position, but, in addition, con tacts TS operate to their opposite positions. The second test position of switch S is provided to permit application of testing potentials to the line 10 at the central station. Thus, with contacts TS1 operated to their front position, the line 18 Will be connected to the central station test equipment and the drop will be isolated from line 10. Contacts TS2, which are connected in series with contacts LS2, open. With contacts TS2 open, capacitor 23 will discharge Y(since there will be no line current through potentiometer 14) andthe transistor 25 will become conductive, in turn energizing the break lamp 28. The lamp 28 will remain illuminated until capacitor 23 is allowed to recharge and reset switch 26 is opened.

While the invention has been described in connection with a specic embodiment thereof and in a specific use,

various modiiications thereof will occur to those skilled aasaaia 47 in the art without departing from the spirit and scope of the invention as set -forth in the appended claims.

Wh?? is, Claimed is.:

l. A signalling circuit for registering signalling currents in a conductive line above and below a predetermined norrnal range of current fiow in said line, comprising first and second unijunction transistors, biasing means comprising means to Supply respective biasing potentials between the emitter and one base of each of`sad unijunction transistors and between both bases of each of said unijunction transistors, the ratios between said biasing potentials supplied to each of said unijunction transistors being selected normally to render both of said first land second unijunction transistors nonconductive, means responsive to the current flow in said line to produce rst and second voltages proportional to the current flew. in said line, means operative in response to said first voltage falling below a value corresponding to a current flow in said line equal to the minimum of said range to alter said ratio between said biasing potentials supplied to said rst unijunction transistor to render said unijunction transistor conductive, means operative in response to said second voltage exceeding a value corresponding toV a current flow in said line equal to the maximum of said range to alter said ratio between said biasing potentials supplied to said second unijunction transistor to render said second unijunction transistor conductive, and first and second signalling means coupled respectively to said first and second unijunction transistors, said first signalling means being operative upon conduction of said first unijunction transistor to register a current flow in said line below said range and said second signalling means being operative upon conduction of said second unijunction transistor to register a current flow in said line above said range.

2. A signalling circuit for registering signalling currents inl a conductive line above and below a predetermined normal range of current flow in said line, comprising first and second unijunction transistors, biasing means comprising means to supply respective biasing potentials between the emitter and one base of each of said unijunction transistors and between both bases of each of said unijunction transistors, the ratios between said biasing potentials supplied to each of said unijunction transistors being selectedto. render both of said first and second unijunction transistors nonco'nductive when the current in said line lies within said normal range, means responsive to the current flow. in said line to produce first and second voltages proportional to the current flow in said line, means operative in'response to said first voltage falling below a valueV corresponding to a current flow in said line equal to the minimum of said range to alter said ratio between saidbiasing'potentials supplied to 'said first unijunction transistor to render saidffirst unijunction transistor conductive, said last mentioned means including first delay means coupled to said first unijunction transistor to prevent conduction thereo'f until the current flow in said line hasV been below the minimum value of said range for a first predetermined time interval, said first delay means including a first capacitive element and a discharging circuit for said rst capacitive element, means operative in response to said second voltage exceeding a value corresponding to a current flow in said line equal to the maximum of said range to alter said ratio between said biasing potentials supplied to said second unijunction transistor to render said second unijunction transistor conductive, said last mentioned means including second delay means coupled to said second unijunction transistor to' prevent conduction thereof until the current flow in said line has been above the maximum value of said range for a second predetermined time interval, said second delay means including a second capacitive element and a charging circuit for said secondcapacitive element, and first andsswnd Sisflalll'ilg` means.V` coupled respectively to Saidf first end ssgnd: unijtltlctgn transistors2 Saidrst Signal.-v

ling means being operative upon conduction of said first unijunction transistor to register a current flow in said line below said range, said second signalling means being operative upon conduction of said second unijunction transistor to register a current flo'w in said line above said range.

3. A signalling circuit for registering signalling currents in a conductive line above and below a predetermined normal range of current ow in said line, comprising first and second unijunction transistors, biasing means arranged to render both of said first and second uni junction transistors nonconductive when the current in said line lies within saidy normal range, first circuit means responsive to the current flow` in said line to produce first and second voltages proportional' to the current flow in said line, means operative in response to said first voltage falling belo'w a value corresponding to a current flow in said line equal to the minimum of said range to. render said first unijunction transistor conductive, said first circuit means including a first diode element arranged to be conductive only when the current flow in said line is at least as great as the minimum of said range, second circuit means operative in response tor said second voltage exceeding a value corresponding to' a current ow in said line equal to the maximum of said range to render said second unijunction transistor conductive, said second circuit means including a second diode element arranged to be conductive only when the current flow in said line exceeds the maximum of said range, and first and second signalling means coupled respectively to said first and second unijunction transistors, said first signalling means being operative upon conduction of said first unijunction transistor to register a current flow in said line below said range, said second signalling means being operative upon conduction of said second unijunction transistor to register a current o'w in said line above said range.

4. A signalling circuit as set forth in claim 3 in which said first circuit means includes a capacitive element coupled to one base of said first unijunction transistor and arrangedvto be charged to a value sufficient to maintain saidfirst unijunction transistor nonconductive when said first diode element is conductive.

5. A signalling circuit as set forth in claim 4 in which said first circuit means provides a discharge time constant for said capacitive. element selected to provide a predetermined time delay iu conduction of said frstunijunction transistor.

6. A signalling circuit as set forth in claim 3 in which said second circuit means fincludes a capacitive element coupled tothe emitter of said second unijunction transistor and arranged to be charged -to a value sufficient to render said second unijunction transistor conductive when said second diode element is conductive.

7. A signalling. circuit as set forth in claim 6 in which said second circuit means provides a charging time constant for said capacitive element selected to provide a predetermined time delay in conduction of` said second unijunction transistor.

8. A signalling circuit as set forth in claim 6 in which said first circuit means includes a second capacitive element coupled to one base of said first unijunction transistor and arranged to be charged to a value sufficient to maintain said first unijunction transistor nonconductive when said first diode element is conductive.

9. A signalling circuit as set forth in claim 8 in which said first and second circuit means provide a discharging time constant and. a charging time constant, respectively, for said first and second capacitive elements, respectively, to prevent conduction ofy said first and second unijunction transistors, respectively, for predetermined time intervals after said first and second diode elements, respectively, become conductive.

l0. A signalling circuit for registering signalling currentsirr a conductive line above and belowl a. Predeter-v mnd nsrmalransei; current How irlsaid line, com-A assente prising first and second unijunction transistors, biasing means arranged to'render both of said first and second unijunction transistors nonconductive when the current in said line lies within said normal range, means responsive to the current fiow in said line to produce first and second voltages proportional to the current flow in said line, means including a first transistor device and operative in response to said first voltage falling below a value corresponding to a current flow in said line equal to the minimum of said range to render said first unijunction transistor conductive, means including a second transistor device and operative in response to said second voltage exceeding a value corresponding to a current fiow in said line equal to the maximum of said range to render said second unijunction transistor conductive, first and second signalling means coupled, respectively, to said first and second unijunction transistors, said first signalling means being operative upon conduction of said first unijunction transistor to register a current fiow in said line below said range, said second signalling means being operative upon conduction of said second unijunction transistor to register a current flow in said line above said range, third signalling means, and means operatively coupled to one of said first and second transistor devices and being responsive to fluctuations in one of said first and second voltages above and below said value thereof corresponding to a current liow in said line equal to a terminal value of said range to operate said third signalling means.

l1. A signalling circuit for registering signalling currents in a conductive line above and below a predetermined normal range o f current iiow in said line, comprising first and second unijunction' transistors, biasing means arranged to render both of said first and second unijunction transistors nonconductive when the current in said line lies within said normal range, means responsive to the current flow in said line to produce first and second voltages proportional to the current fiow in said line, first circuit means operative in response to said first voltage falling below a value corresponding to a current flow in said line equal to the minimum of said range to render said first unijunction transistor conductive, said first circuit means including first'delay means arranged to delay conduction of said first unijunction transistor for a predetermined time interval after the current flow in said line has dropped below said minimum of said range, second circuit means operative in response to said second voltage exceeding a value corresponding to a current flow in said line equal to the maximum of said range to render said second unijunction transistor conductive, said second circuit means including second delay means arranged to delay conduction of said second unijunction transistor for a predetermined time interval after the current flow in said line has risen above said maximum of said range, first and second signalling means coupled, respectively, to said first and second unijunction transistors, said first signalling means being operative upon conduction of said first unijunction transistor to register a current fiow in said line below said range, said second signalling means being operative upon conduction of said second unijunction transistor to register a current flow in said line above said range, third signalling means, and third circuit means responsive to fluctuations in said first voltage above and below said value thereof corresponding to a current flow in said line equal to the minimum of said range to operate said third signalling means, said third circuit means beng coupled to said first circuit means and being arranged so as not to be subject to said first time delay means.

12. A signalling system as set forth in claim 11, comprising manually operable means arranged, when operated, to prevent conduction of said first and second unijunction transistors and to render said third signalling' means continuously operative independent of current fiow in said line.

13. A signalling circuit for registering signalling currentsY in a conductive line above and below a predeterd mined normal range of current flow in said line, comprising first and second unijunction transistors, means responsive to the current liow in said line to produce first and second voltages proportional to the current flow in said line, first circuit means including a first capacitive element having a predetermined discharging time con-y stant, means to apply said first voltage to said first circuit means, said first circuit means being arranged toy charge said first capacitive element when said first voltage at least equals a value corresponding to a current fiow in said line equal to the minimum of said range and to discharge said first capacitive element for lower values of said rst voltage, first biasing means for the first unijunction transistor, said first biasing means including said first capacitive element and being arranged to render said first unijunction transistor conductive only when the charge on said first capacitive element has fallen to a predetermined level below the full charge thereof, first signalling means coupled to said first unijunction transistor and arranged to register conduction thereof as n signal of current fiow in said line below said normal range, second circuit means including a second capacitive element'having a predetermined charging time constant, means to apply said second Voltage to said second circuit means, said second circuit means being arranged to charge said second capacitive element when said second voltage exceeds a value corresponding to a current flow in said line equal to the maximum of said range and to discharge said second capacitive element for lower values of said second voltage, second biasing means for said second unijunction transistor, said second biasing means being arranged so that said second unijunction transistor is normally nonconductive, means intercoupling said second capacitive element and said second unijunction transistor to render the latter conductive when the charge on said second capacitive element exceeds a predetermined value, and second signalling means coupled to said second unijunction transistor and arranged to register conduction thereof as a signal of current fiow in said line above said normal range.

14. A signalling circuit as set forth in claim 13 in which said rst capacitive element has a charging time constant shorter than said predetermined discharging time constant thereof.

15. A signalling circuit as set forth in claim 13 in which said discharging time constant of said first capacitive element and said charging time constant of said second capacitive element are adjustable.

16. A signalling circuit for registering signalling currents in a conductive line above and below a predetermined normal range of current flow in said line, comprising first and second yunijunction transistors, means responsive to the current flow in said line to produce first and second voltages proportional to the current iiow in said line, first circuit means including a first capacitive element having a relatively short charging time constant and a relatively long discharging time constant, said first capacitive element being coupled to one base of said first unijunction transistor, means to apply a first fixed potential to the emitter of said first unijunction transistor and a second fixed potential to the other base of said first unijunction transistor, means to apply said first voltage to said first circuit means, said first circuit means being arranged to charge said first capacitive element when said rst Voltage at least equals a value corresponding to a current flow in said line equal to the minimum of said range and to discharge said first capacitive element for lower values of said first voltage, rst biasing means for said first unijunction transistor, said first biasing means including said first capacitive element and being arranged to render said first unijunction transistor conductive only when the charge on said rst capacitive element has fallen to a predetermined level below the full charge assente 1l thereof, rst signalling means coupled to said rst unijunction transistor4 and arranged to register conduction thereof as a signal of current iiow in said line belowsaid, normal range, second circuit means including a second capacitive element having a predetermined. charging time.y constant, said second capacitive element being coupled to the emitter of said second unijunction transistor, means. to apply thirdl and fourth fixed potentials to the respective bases of said second unijunction transistor, means to apply said second voltage to said second circuit means, said second circuit means being arranged to charge said second capacitive element when said second voltage exceeds a value corresponding to a current fiow in said line equal to the maximum of said range and to discharge said second capacitive element for lower values ofV said second voltage, said third and fourth fixed potentials being selected so that said second unijunction transistor is normally nonconductive and remains nonconductive until the charge on said second capacitive element exceeds a predetermined value, and second signalling means coupled to said second unijunction transistor and arrangedy to register conduction thereof as a signal of current iiow in said line above said normal range.

17. A signalling circuit for registering signalling currents in a conductive line above and below a predetermined noinial range of current flow in said line, com prising first and second unijunction transistors, means responsive to the current flow in said liney to produce first and second voltages proportional to the current-flow in said line, first circuit means including a first capacitive element havingL a relatively short charging time constant and a relatively long discharging time constant, means toy apply said first voltage to said first circuit means, said first circuit means including a first diode arranged to be conductive only when said first voltage at least equals a value corresponding to a current fiow in said line equaly to the minimum of said range, said first circuit means being arranged to charge said first capacitive element when said first diode is conductive and to discharge said first capacitive element when said first diode is non-conductive, first biasing means for said first unijunction transistor, said first biasing means including said firstV capacitive element and being arranged to render said first-unijunction transistor conductive only whenvthe charge on said first capacitive element has fallen to a predetermined level below the full charge thereof, first signalling means coupled to said first unijunction transistor and arranged to register conductionl thereof as asignal of current flow in said line below said normal range, secondV circuit means including a secondl capacitive element having a predetermined charging time constant, means to apply said second voltage to said second circuit means, said` second circuit means including a second diode arranged to be conductive only when said second voltage exceeds a value corresponding `to a current fiow in said line equal to the maximum of said range, said second circuit means being arranged to charge said second capacitive elementl when said second diode is conductive and to discharge said secondcapacitive element when said second diode isnonconductive, second biasing means for said second unijunction transistor, said second biasing means being arranged so that said second unijunction transistor is4 normally nonconductive, means intercoupling said second capacitive element and said second unijunction transistor to render the latter conductive when the charge on said second capacitive element exceeds a predetermined value,`

and second signal-ling means coupled to said second unijunction transistor and arranged to register conduction thereof as a signal of current flow in said line above said normal range.

18. A signalling circuit for registering signalling currents in a conductive line above and below a predetermined-normal range of current flow in said line, comprisingl firstl and second unijunction transistors, means r esponsive tothe-currentfiow. in-said line to produce first and second voltages proportional to the current flow in said line, first circuit means including a first capacitive element` havingaI relatively short charging time constant and a relatively long discharging time constant, means to apply said first voltage to said first circuit means, said first circuit means being arranged to charge said first capacitive element when said first voltage at least equals a valve corresponding to a current flow in said line equal to the minimum of said range and to discharge said first capacitive element for lower values of said first voltage, first biasing means for Said first unijunction transistor, Said first biasing means including said first capacitive element and being arranged to render said first unijunction transistorrconductive only when the charge on said first capacitive element has fallen to a predetermined level below the full charge thereof, first signalling means coupled to said first unijunction transistor and arranged to registery conduction thereof as a signal of current fiow on said line below said normal range, second circuit meansv including a second capacitive element having a predetermined charging time constant, means to apply said second;

means intercoupling said second capacitive element andsaid second unijunction transistor to render the latter conductive when the charge on said second capacitive element exceeds a predetermined value, second signallingmeans coupled to said second unijunction transistor andy arranged to register conduction thereof as a signal of current flow in said line above said normal range, third signalling means, and third circuit means intercoupling said first circuit means and said third signalling means and arranged to operate said third signalling means when said first voltage falls below said value thereof corresponding to a current flow in said line equal to the minimum of said range.

19. A signalling circuit for registering signalling currents in a conductive line above and below a predetermined normal range of current fiow in said line, comprising first and second unijunction transistors, means responsivepto the current flow in said line to produce first andsecond voltages proportional to the current flow in saidy line, first circuit means including a first capacitive element` coupled to one base of, said first unijunction transistorl and having a relatively short chargingl time constantv and a relatively long discharging time constant, means to apply said first voltage to said first circuit means, saidl first circuit means being arranged to charge said first capacitive element when said first voltage at least equals a value corresponding to a current fiow in said line equal to the minimum of said range and to discharge saidl first capacitive element for lower values of said first voltage, first biasing means for said first unijunction transistor, said first biasing means including said first capacitive element, a source of a reference potential coupled to the other base of said first unijunction transistor and a source of a first fixed potential coupled to the emit-ter of said first unijunction transistor, said first biasingmeans being arranged to render said first unijunction transistor conductive only when the charge on said first capacitive element has fallen to a predetermined level below the full charge thereof, first signalling means including a first lamp having an energizing circuit coupled to said first unijunction transistor and arranged to become illuminated as a signal of current ow in said line below said normal range, second circuit means including a second capacitive element coupled to the emitterof. said` second unijunction transistor and having a predetermined charging time constant, means to apply said second voltage to said second circuit means, said second circuit means being arranged to charge said second capacitive element when said second Voltage exceeds a yvalue corresponding to a current flow in said line equal to the maximum of said range and to discharge said second capacitive element for lower values of said second voltage, second biasing means for said second unijunction transistor, said second biasing Ameans including said second capacitive element, a connection between said source of reference potential and one base of said second unijunction transistor and a source of a second fixed potential coupled to the other base of said second unijunction transistor, said second biasing means being arranged so that said second unijunction transistor is normally nonconductive but becomes conductive when the charge on said second capacitive element exceeds a predetermined value, second signalling means including a second lamp having an energizing circuit coupled to said second unijunction transistor and arranged to become il luminated as a signal of current flow" in said line above said normal range, third signalling means including a third lamp and third circuit means intercoupling said first circuit means and said third signalling means and arranged to illuminate said third lamp when said first -voltage falls below said value thereof corresponding to a current flow in said line equal to the minimum of said range and to extinguish said third lamp when said first voltage at least equals said last mentioned value thereof.

20. A signalling circuit for registering signalling currents in a conductive line above and below a predetermined normal range of current fiow in said line, comprising a first transistor, a first diode element coupled to said :first transistor and arranged to prevent conduction of said first transistor unless at least a first potential of predetermined minimum value is applied to said first dide, first adjustable means to derive a first voltage proportional to the current fiow in said line and to apply said first voltage to an electrode of said first transistor in a sense to cause said first potential to be applied to said rst diode, said first adjustable means being arranged so that said first potential equals said predetermined minimum value thereof when said current flow in said line equals the minimum current of said normal range, first circuit means including a first capacitor coupled to an electrode of said first transistor and arranged to charge when said first transistor is conductive and to discharge when said first transistor is nonconductive, said first circuit means afording a predetermined discharging time constant for said first capacitor, a first unijunction transistor, means intercoupling said first capacitor and one base of said first unijunction transistor thereby to apply a first biasing potential to the bases of said first unijunction transistor, a source of a first fixed voltage, means to apply said first fixed voltage to the emitter of said first unijunction transistor, said first fixed voltage being sufcient to render said first unijunction transistor conductive when the charge on said first capacitor falls below a predetermined proportion of the full charge thereof, first signalling means coupled to said first unijunction transistor and being arranged to register conduction of said first unijunction transistor as a signal of current iiow in said line below said normal range, a second transistor, a second diode element coupled to said second transistor and arranged to prevent conduction of said second transistor unless at least a second potential of predetermined minimum value is applied to said second diode, second adjustable means to derive a second voltage proportional to the current flow in said line and to apply said second voltagev to an electrode of said second transistor in a sense to cause said second potential to be applied to said second diode, said second adjustable means being arranged so that said second potential at least equals said predetermined minimum value thereof when said current ow in said line exceeds the maximum current of said normal range, second circuit means including a'second capacitor coupled to van electrode of Vsaid second transistor and arranged to charge when said second transistor is conductive and to discharge when said second transistor is nonconductive, said second circuit means afiording a predetermined charging timeconstant for said 'second capacitor, a second unijunction transistor, means intercoupling said second capacitor and the emitter of said second unijunction transistor, a source of a second biasing potential, means to apply said second biasing potential to the bases of said second unijunction transistor, said second biasing potential being sufliciently high as to prevent conduction of said second unijunction transistor until the charge on said second capacitor exceeds a predetermined value, and second signalling means coupled to said second unijunction transistor and being arranged to register conduction of said second unijunction transistor as a signal of current flow in said line above said normal range.

2l. A signalling circuit for registering signalling currents in a conductive line above and below a predetermined normal range of current flow in said line, comprising a first transistor, a first diodel element coupled to said first transistor and arranged to prevent conduction of said first transistor unless at least a first potential of predetermined minimum value is applied toV said first diode, first adjustable means to derive a first voltage proportional to the current flow in said line and to apply said first voltage to an electrode of said first transistor n a sense to cause said first potential to be applied to said first diode, said first adjustable means being arranged so that said first potential equals said predetermined minimum value thereof when said current flow in said line equals the minimum current of said normal range, first circuit means including a first capacitor coupled to an electrode of said first transistor and arranged to charge when said first transistor is conductive and to discharge when vsaid first transistor is nonconductive, said first circuit means affording a relatively short charging time constant for said first capacitor and an adjustable discharging time constant for said first capacitor, a first unijunction transistor, means to apply `a reference potential to one base of said first uninjunction transistor, means intercoupling said first capacitor and the other base of said rst unijunction transistor thereby to apply a first biasing potential to the bases of said first unijunction transistor, a source of a first fixed voltage, means to apply said first fixed voltage to the emitter of said first unijunction transistor, said first fixed voltage being sufficient to render said first unijunction transistor conductive when the charge on said first capacitor falls below a predetermined proportion of the full charge thereof, first signalling means coupled to said first unijunction transistor and being arranged to register conduction of' said first unijunction transistor as a signal of current flow in said line below said normal range, a second transistor, a second diode element coupled to said second transistor and arranged to prevent conduction of said second transistor unless at least a second potential of predetermined minimum value is applied to said second diode, second adjustable means to'derive a second voltage proportional to the current fiow in said line and to apply said second voltage to an electrode of said second transistor in a sense to cause said second potential to be applied to said second diode, said second adjustable means being arranged so that said second potential at least equals said predetermined minimum value thereof when said current flow in said line exceeds the maximum current of said normal range, second circuit means including a second capacitor coupled to an electrode of said second transistor and arranged to charge when said second transistor is conductive and to discharge when said second transistor is nonconductive, said second circuit means affording an adjustable charging time constant for said second capacitor, a second unijunction transistor,

means intercoupling saidY second capacitor and` the emitter of said second unijunction transistor, a source of av second biasing potential, means to apply said second biasing potential to the bases of said second unijunction transistor, said second biasing potential being sufficiently high as to prevent conduction of said second unijunction transistor until the charge on said second capacitor exceeds a predetermined value, and second signalling means coupled to said second unijunction transistor and being arranged to register conduction of said second unijunction transistor as a signal of current fiow in said line above said normal range.

22. A signalling circuit for registering signalling currents in a conductive line above and below a predetermined normal range of current flow in said line, comprising a first transistor, a first diode element coupled to said first transistor and arranged to prevent conduction of` said first transistor unlessv at least a first potential of predetermined minimum value is applied to said first diode, first adjustable means to derive a first voltage proportional to thev current fiow in. said line and to apply said first voltage to an electrode of said' first transistor in a sense to cause said first potential to be applied to said first diode, said first adjustable means being arranged so that said first potential equals said predetermined minimum value thereof when said current flow in said line equals the minimum current of said normal range, first circuit means including a first capacitor coupled to an electrode of said first transistor and arranged to charge when said first transistor is conductive and to discharge when said first transistor is nonconductive, said first circuit means affording a reliatively short charging time constant for said first capacitor and a relatively long discharging time constant for said first capacitor, a first unijunction transistor, means intercoupling said first capacitor and one base of said first unijunction transistor thereby to apply a first biasing potential to the bases of said first unijunction transistor, a source of a first fixed voltage, means to apply said first fixed voltage to the emitter of said first unijunction transistor, said first fixed voltage being sufficient to render said first unijunction transistor conductive when the charge on said first capacitor falls below a predetermined proportion of the full charge thereof, first sig` nalling means coupled to said first unijunction transistor and being arranged to register conduction of said first unijunction transistor as a signal of current flow in said line below said normal range, a second transistor, a second diode element coupled to said second transistor and arranged to prevent conduction of said second transistor unless at least a second potential of predetermined minimum value is applied to said second diode, second adjustablemeans to derive a second voltage proportional to the current ow in said line and to apply said second voltage to an electrode of said second transistor in a sense to cause said second potential to be applied to said second diode, said second adjustable means being arranged so that said second potential at least equals said predetermined minimum value thereof when said current flow in said line exceeds the maximum current of said normal range, second circuit means including a second capacitor coupled to an electrode of said second transistor and arranged to charge when said second transistor is conductive and to discharge when said second transistor is nonconductive, said second circuit means affording a relatively long charging time constant for said second capacitor, a second unijunction transistor, means intercoupling said second capacitor and the emitter of said second unijunction transistor, a source of a second biasing potential, means to apply said second biasing potential to the bases of said second uninjunction transistor, said second biasing potential being sufiiciently high as to prevent `conduction of said second unijunction transistor unlessthe charge on said second capacitor exceeds a predetermined value, second signallingfmeans'coupled to saidsecond unijunction transistor and beingarranged to register. conductionv of said second unijunction transistor as` a signal of current fiow in said line above saidtnormalrange, a third transistor coupled to said first transistor and being arranged to be in opposite condition to said first transistor, and third signalling means coupled to said third transistor, said third signalling means being arranged to be operative only when said third transistor is conductive.

23. A signalling circuit for registering signalling currents in a conductive line above and below a predetermined' normal range of current flow in said line, comprising a first transistor, a first diode element coupled to said first transistor and arranged to prevent conduction of said first transistor unless at least a first potential of predetermined minimum value is applied to said first diode, first potentiometer means coupled to said line and arranged to derive a first voltage proportional to the current fiow in said line and to apply said first voltage to an electrode of said first transistor in a sense to cause Saidv first potential to be applied to said first diode, said first potentiometer means being adjusted so that said first potential equals said predetermined minimum value thereof` when, said current flow in said line equals the minimum current of said normal range, first circuit means including a` first capacitor coupled to an electrode of said first transistor and arranged to charge when saidk first transistor is conductive and to discharge when said first transistor is nonconductive, said rst circuit means affording a relatively short charging time constant for said first capacitor and an adjustable discharging time constant for said first capacitor, first normally open switch means arranged, when closed, to intercouple said first capacitor. and a source of charging potential thereby to maintain full charge on said first capacitor irrespective of` decreases in line current, a first unijunction transistor, means. intercoupling said first capacitor and one base of said` first unijunction transistor thereby to apply a first biasing potential to the bases of said first unijunction transistor, a source of a first fixed voltage, means to apply said: first fixed voltagc to the emitter of said first unijunction transistor, said first fixed voltage being sufficient to render said first unijunction transistor conductive when the charge on said first capacitor falls below a predetermined proportion of the full charge thereof, first signalling means coupled to said first unijunction transistor and being arranged to register conduction of said first unijunction transistor as a signal of current fiow in said line below said'normal range, a secondtransistor, asecond diode element coupled to said second transistor and arranged to prevent conduction of said' second` transistor unless at least a second potential of predetermined minimum value is applied to said second diode, second potentiometer means coupled to said'line. and arranged to derive a second voltage proportional to the current fiow in said line and to apply said second voltage to an electrode of` said second transistor in a sense to cause said second potential to be applied to said seconddiode, said second adjustable means being arranged so that said secondV potential at least equals said predetermined minimum value thereof when said current flow inI said line exceeds the maximum current: of said normal range, second circuit means including a second capacitor cou pled to an electrode of said second transistor and arranged to charge when said second transistor is conductive andtodischarge when said second transistor is nonconductive, said second circuit means affording an adjustable charging time constant for said second capacitor, a second'unijunction transistor, means intercoupling said second capacitor and the emitter of said second unijunction transistor, a source of a second biasing potential, means to `apply said second biasing potential to the bases of said' second unijunction transistor, said second biasing potential'beingl sufficiently high as to prevent conduction of said second unijunction transistor until thecharge second normally closed switch means included in said last mentioned means and arranged, when open, to prevent conduction of said second unijunction transistor,

second signalling means coupled to said second unijunction transistor and being arranged to register conduction of said second -unijunction transistor as a signal of cur- -rent -ow in said line above said norm-al range, a third transistor coupled to said first transistor and being arranged to be in opposite condition to said tirst transistor, third signalling means coupled to said third transistor, said third signalling means being arranged to be operative normally only when said third transistor is conductive, and third normally unoperatedv switch means arranged, when operated, to maintain operation of said third signalling means irrespective of the current iiow in said line. f

24. A signalling circuit as set forth in claim 23, comprising fourth normally closed switch means in series with said line; and fifth normally closed switch means connected in series with said first switch means and arranged, when open, to prevent application of said charging potential to said rst capacitor through said first switch means; all of said switch means forming part of a three position ganged switch; in a normal position of said ganged switch said tirst switch means being open, said second switch means being closed, said third switch means being unoperated, said fourth switch means being closed, and said fth switch means being closed; in a rst test position of said switch said iirst switch means being closed, said second switch means being open, said third switch means being operated, said fourth switch means being closed, and said -fth switch means being closed; in a second test position of said switch said iirst switch means being closed, said second switch means being open, said third switch means being operated, said fourth switch means being open, and said fth switch means being open.

References Cited in the tile of this patent UNITED STATES PATENTS 20 1,840,637 Reid Jan. 12, 1932 2,719,289 Borstow Sept. 27, 1955 2,814,033 Muehter Nov, 19, 1957 

